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This version: Apr. 7. 1999
Semiconductor MSC23836C-xxBS20/DS20
8,388,608-word x 36-bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE
DESCRIPTION
The MSC23836C-xxBS20/DS20 is an 8,388,608-word x 36-bit CMOS dynamic random access memory module which is composed of sixteen 16Mb(4Mx4) DRAMs in SOJ packages and four 8Mb(4Mx2) DRAMs in SOJ packages mounted with twenty decoupling capacitors. This is a 72-pin single in-line memory module. This module supports any application where high density and large capacity of storage memory are required.
FEATURES
* 8,388,608-word x 36-bit organization * 72-pin Single In-Line Memory Module MSC23836C-xxBS20 : Gold tab MSC23836C-xxDS20 : Solder tab * Single 5V power supply, 10% tolerance * Input : TTL compatible * Output : TTL compatible, 3-state * Refresh : 2048cycles/32ms * /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability * Fast page mode capability * Multi-bit test mode capability
PRODUCT FAMILY
Access Time (Max.) tRAC MSC23836C-60BS20/DS20 MSC23836C-70BS20/DS20 60ns 70ns tAA 30ns 35ns tCAC 15ns 20ns Cycle Time (Min.) 110ns 130ns Power Dissipation (Max.) Operating 5995mW 5500mW Standby 110mW
Family
Semiconductor
MSC23836C
MODULE OUTLINE
MSC23836C-xxBS20/DS20
107.950.2*1 3.38Typ. 101.19Typ. (Unit : mm) 9.3Max.
3.18 25.40.2
Typ. Typ. 10.16 6.35 2.03Typ. 6.35Typ.
1 1.270.1 R1.57 6.35 95.25 1.04Typ.
72
3.17Min. +0.1 -0.08
5.71Min.
1.27
*1 Tolerance over 14.5mm from bottom edge is 0.5.
Semiconductor
MSC23836C
PIN CONFIGURATION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Presence Detect Pins Pin No. 67 68 69 70 Pin Name PD1 PD2 PD3 PD4 -60 NC VSS NC NC -70 NC VSS VSS NC Pin Name VSS DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 VCC NC A0 A1 A2 A3 A4 A5 A6 Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name A10 DQ4 DQ22 DQ5 DQ23 DQ6 DQ24 DQ7 DQ25 A7 NC VCC A8 A9 /RAS3 /RAS2 DQ26 DQ8 Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Pin Name DQ17 DQ35 VSS /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 NC /WE NC DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin Name DQ12 DQ30 DQ13 DQ31 VCC DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC VSS
Semiconductor
MSC23836C
BLOCK DIAGRAM
A0-A10 /RAS0 /CAS0 /WE A0-A10 /RAS /CAS /WE VCC A0-A10 /RAS /CAS /WE VCC DQ DQ DQ DQ /OE VSS DQ DQ DQ DQ /OE VSS DQ0 DQ1 DQ2 DQ3 DQ A0-A10 DQ /RAS DQ /CAS DQ /WE /OE VSS VCC DQ A0-A10 DQ /RAS DQ /CAS DQ /WE /OE VSS VCC A0-A10 /RAS /CAS /WE VCC A0-A10 /RAS /CAS /WE VCC DQ DQ DQ DQ /OE VSS DQ DQ DQ DQ /OE VSS DQ18 DQ19 DQ20 DQ21 DQ A0-A10 DQ /RAS DQ /CAS DQ /WE /OE VSS VCC DQ A0-A10 DQ /RAS DQ /CAS DQ /WE /OE VSS VCC
/RAS2 /CAS2
DQ4 DQ5 DQ6 DQ7
DQ22 DQ23 DQ24 DQ25
A0-A10 DQ1 /RAS DQ2 /CAS1 /CAS2 /WE /OE VCC VSS
DQ8 DQ17
DQ1 A0-A10 DQ2 /RAS /CAS1 /CAS2 /OE /WE VSS VCC
A0-A10 DQ1 /RAS DQ2 /CAS1 /CAS2 /WE /OE VCC VSS
DQ26 DQ35
DQ1 A0-A10 DQ2 /RAS /CAS1 /CAS2 /OE /WE VSS VCC
A0-A10 /RAS /CAS /WE VCC A0-A10 /RAS /CAS /WE VCC /RAS1 /CAS1 VCC VSS C1-C20
DQ DQ DQ DQ /OE VSS DQ DQ DQ DQ /OE VSS
DQ9 DQ10 DQ11 DQ12
DQ A0-A10 DQ /RAS DQ /CAS DQ /WE /OE VSS VCC DQ A0-A10 DQ /RAS DQ /CAS DQ /WE /OE VSS VCC
A0-A10 /RAS /CAS /WE VCC A0-A10 /RAS /CAS /WE VCC
DQ DQ DQ DQ /OE VSS DQ DQ DQ DQ /OE VSS
DQ27 DQ28 DQ29 DQ30
DQ A0-A10 DQ /RAS DQ /CAS DQ /WE /OE VSS VCC DQ A0-A10 DQ /RAS DQ /CAS DQ /WE /OE VSS VCC /RAS3 /CAS3
DQ13 DQ14 DQ15 DQ16
DQ31 DQ32 DQ33 DQ34
Semiconductor
MSC23836C
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature * Ta = 25C Symbol VIN, VOUT VCC IOS PD * TOPR TSTG Rating -0.5 to 7.0 -0.5 to 7.0 50 20 0 to 70 -40 to 125 Unit V V mA W C C
Recommended Operating Conditions ( Ta = 0C to 70C ) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min. 4.5 0 2.4 -0.5 Typ. 5.0 0 Max. 5.5 0 VCC + 0.5 0.8 Unit V V V V
Capacitance ( VCC = 5V 10%, Ta = 25C, f = 1 MHz ) Parameter Input Capacitance (A0 - A10) Input Capacitance (/WE) Input Capacitance (/RAS0 - /RAS3) Input Capacitance (/CAS0 - /CAS3) I/O Capacitance (DQ0 - DQ35) Symbol CIN1 CIN2 CIN3 CIN4 CI/O Typ. Max. 135 155 43 50 26 Unit pF pF pF pF pF
Semiconductor
MSC23836C
DC Characteristics (VCC = 5V 10%, Ta = 0C to 70C ) Parameter Output High Voltage Output Low Voltage Input Leakage Current Symbol VOH VOL ILI Condition IOH = -5.0mA IOL = 4.2mA 0V VIN 6.5V; All other pins not under test = 0V DQ disable 0V VOUT VCC /RAS, /CAS cycling, tRC = Min. /RAS, /CAS = VIH ICC2 /RAS, /CAS VCC -0.2V /RAS cycling, /CAS = VIH, tRC = Min. /RAS cycling, /CAS before /RAS /RAS = VIL, /CAS cycling, tPC = Min. -60 Min. 2.4 0 -200 Max. VCC 0.4 200 Min. 2.4 0 -200 -70 Max. VCC 0.4 200 Unit V V A Note
Output Leakage Current Average Power Supply Current (Operating) Power supply current (Standby) Average Power Supply Current (/RAS only refresh) Average Power Supply Current (/CAS before /RAS refresh) Average Power Supply Current (Fast Page Mode)
ILO
-20
20
-20
20
A
ICC1
-
1090 40 20
-
1000 40 20
mA mA mA
1, 2
1
ICC3
-
1090
-
1000
mA
1, 2
ICC6
-
1090
-
1000
mA
1, 2
ICC7
-
910
-
820
mA
1, 3
Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while /RAS = VIL. 3. The address can be changed once or less while /CAS = VIH.
Semiconductor
MSC23836C
AC Characteristics (1/2) (VCC = 5V 10%, Ta = 0C to 70C ) Note: 1, 2, 3, 9, 10 Parameter Random Read or Write Cycle Time Fast Page Mode Cycle Time Access Time from /RAS Access Time from /CAS Access Time from Column Address Access Time from /CAS Precharge Output Low Impedance Time from /CAS /CAS to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period /RAS Precharge Time /RAS Pulse Width /RAS Pulse Width (Fast Page Mode) /RAS Hold Time /CAS Precharge Time (Fast Page Mode) /CAS Pulse Width /CAS Hold Time /CAS to /RAS Precharge Time /RAS Hold Time from /CAS Precharge /RAS to /CAS Delay Time /RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time Column Address Hold Time Column Address to /RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to /RAS Symbol tRC tPC tRAC tCAC tAA tCPA tCLZ tOFF tT tREF tRP tRAS tRASP tRSH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH -60 Min. 110 40 0 0 3 40 60 60 15 10 15 60 10 35 20 15 0 10 0 15 30 0 0 0 Max. 60 15 30 35 15 50 32 10K 100K 10K 45 30 Min. 130 45 0 0 3 50 70 70 20 10 20 70 10 40 20 15 0 10 0 15 35 0 0 0 -70 Max. 70 20 35 40 20 50 32 10K 100K 10K 50 35 Unit ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 8 5 6 4, 5, 6 4, 5 4, 6 4 4 7 3 Note
Semiconductor
MSC23836C
AC Characteristics (2/2) (VCC = 5V 10%, Ta = 0C to 70C ) Note: 1, 2, 3, 9, 10 Parameter Write Command Set-up Time Write Command Hold Time Write Command Pulse Width Write Command to /RAS Lead Time Write Command to /CAS Lead Time Data-in Set-up Time Data-in Hold Time /CAS Active Delay Time from /RAS Precharge /RAS to /CAS Set-up Time (/CAS before /RAS) /RAS to /CAS Hold Time (/CAS before /RAS) /WE to /RAS Precharge Time (/CAS before /RAS) /WE Hold Time from /RAS (/CAS before /RAS) /RAS to /WE Set-up Time (Test Mode) /RAS to /WE Hold Time (Test Mode) Symbol tWCS tWCH tWP tRWL tCWL tDS tDH tRPC tCSR tCHR tWRP tWRH tWTS tWTH -60 Min. 0 10 10 15 15 0 15 10 10 20 10 10 10 20 Max. Min. 0 15 10 20 20 0 15 10 10 20 10 10 10 20 -70 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note
Semiconductor
MSC23836C
Notes: 1. A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles (/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5ns. 3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2TTL loads and 100pF. 5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met. tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met. tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then the access time is controlled by tAA. 7. tOFF(Max.) define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 4-bit parallel test function. CA0 and CA1 are not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by a /RAS only refresh or /CAS before /RAS refresh cycle. 10. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.

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